| 1. Introduction to Digital Logic |
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1.1 Background |
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1.2 Digital Logic |
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1.3 Verilog |
| 2. Basic Logic Gates |
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2.1 Truth Tables and Logic Equations |
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The Three Basic Gates |
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Four New Gates |
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2.2 Positive and Negative Logic: De Morgan’s Theorem |
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2.3 Sum of Products Design |
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2.4 Product of Sums Design |
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Verilog Examples |
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Example 1 – 2-Input Gates
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Example 2 – Multiple Input Gates
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Problems |
| 3. Boolean Algebra and Logic Equations |
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3.1 Boolean Theorems |
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One-Variable Theorems |
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Two- and Three-Variable Theorems |
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3.2 Karnaugh Maps |
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Two-Variable K-Maps |
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Three-Variable K-Maps |
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Four-Variable K-Maps |
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3.3 Computer Mimimization Techniques |
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Tabular Representations |
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Prime Implicants |
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Essential Prime Implicants |
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Verilog Examples |
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Example 3 – Majority Circuit
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Example 4 – 2-Bit Comparator
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Problems |
| 4. Implementing Digital Circuits |
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4.1 Implementing Gates |
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4.2 Transistor-Transistor Logic (TTL) |
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4.3 Programmable Logic Devices (PLDs and CPLDs) |
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A 2-Input, 1-Output PLD |
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The GAL 16V8 |
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CPLDs |
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4.4 Field Programmable Gate Arrays (FPGAs) |
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Verilog Examples |
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Example 5 – Map Report
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Problems |
| 5. Combinational Logic |
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5.1 Multiplexers |
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2-to-1 Multiplexer |
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4-to-1 Multiplexer |
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Quad 2-to-1 Multiplexer |
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Verilog Examples |
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Example 6 – 2-to-1 Multiplexer: if Statement
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Example 7 – 4-to-1 Multiplexer: Module Instantiation
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Example 8 – 4-to-1 Multiplexer: case Statement
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Example 9 – A Quad 2-to-1 Multiplexer
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Example 10 – Generic Multiplexer: Parameters
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Example 11 – Glitches
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5.2 7-Segment Displays |
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Verilog Examples |
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Example 12 – 7-Segment Decoder: Logic Equations
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Example 13 – 7-Segment Decoder: case Statement
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Example 14 – Multiplexing 7-Segment Displays
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Example 15 – 7-Segment Displays: x7seg and x7segb
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5.3 Comparators |
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Cascading Comparators |
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TTL Comparators |
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Verilog Examples |
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Example 16 – 4-Bit Comparator Using a Verilog Task
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Example 17 – N-Bit Comparator Using Relational Operators
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5.4 Decoders and Encoders |
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Decoders |
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TTL Decoders |
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Encoders |
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Priority Encoders |
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TTL Encoders |
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Verilog Examples |
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Example 18 – 3-to-8 Decoder: Logic Equations
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Example 19 – 3-to-8 Decoder: for Loops
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Example 20 – 8-to-3 Encoder: Logic Equations
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Example 21 – 8-to-3 Encoder: for Loops
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Example 22 – 8-to-3 Priority Encoder
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5.5 Code Converters |
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Binary-to-BCD Converters |
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Shift and Add 3 Algorithm |
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Gray Code Converters |
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Verilog Examples |
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Example 23 – 4-Bit Binary-to-BCD Converter: Logic Equations
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Example 24 – 8-Bit Binary-to-BCD Converter: for Loops
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Example 25 – 4-Bit Binary to Gray Code Converter
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Example 26 – 4-Bit Gray Code to Binary Converter
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Problems |
| 6. Arithmetic Circuits |
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6.1 Adders |
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Half Adder |
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Full Adder |
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Carry and Overflow |
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TTL Adder |
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Verilog Examples |
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Example 27 – 4-Bit Adder: Logic Equations
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Example 28 – 4-Bit Adder: Behavioral Statements
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Example 29 – N-Bit Adder: Behavioral Statements
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6.2 Subtractors |
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Half Subtractor |
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Full Subtractor |
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An Adder/Subtractor Circuit |
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Verilog Examples |
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Example 30 – 4-Bit Adder/Subtractor: Logic Equations
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Example 31 – N-Bit Subtractor: Behavioral Statements
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6.3 Shifters |
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Verilog Examples |
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Example 32 – 4-Bit Shifter
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6.4 Multiplication |
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Binary Multiplication |
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Signed Multiplication |
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Verilog Examples |
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Example 33 – Multiplying by a Constant
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Example 34 – A 4-bit Multiplier
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6.5 Division |
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Binary Division |
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Verilog Examples |
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Example 35 – An 8-bit Divider using a Task
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6.6 Arithmetic Logic Unit (ALU) |
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Verilog Examples |
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Example 36 – 4-Bit ALU
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Problems |
| 7. Sequential Logic |
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7.1 Latches and Flip-Flops |
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SR Latch |
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Clocked SR Latch |
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D Latch |
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Edge-Triggered D Flip-Flop |
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Verilog Examples |
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Example 37 – Edge-Triggered D Flip-Flop
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Example 38 – Edge-Triggered D Flip-Flop with Set and Clear
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Example 39 – D Flip-Flops in Verilog
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Example 40 – D Flip-Flop with Asynchronous Set and Clear
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Example 41 – Divide-by-2 Counter
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7.2 Registers |
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Verilog Examples |
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Example 42 – 1-Bit Register
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Example 43– 4-Bit Register
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Example 44 – N-Bit Register
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7.3 Shift Registers |
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4-Bit Ring Counter |
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Verilog Examples |
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Example 45 – Shift Registers
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Example 46 – Ring Counter
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Example 47 – Debounce Pushbuttons
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Example 48 – Clock Pulse
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7.4 Counters |
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Arbitrary Waveform |
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Verilog Examples |
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Example 49 – 3-Bit Counter
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Example 50 – Modulo-5 Counter
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Example 51 – N-Bit Counter
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Example 52 – Clock Divider: Modulo-10K Counter
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Example 53 – Arbitrary Waveform
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7.5 Pulse-Width Modulation (PWM) |
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Controlling the Speed of a DC Motor using PWM |
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Controlling the Position of a Servo using PWM |
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Verilog Examples |
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Example 54 – Pulse-Width Modulation (PWM)
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Example 55 – PWM Signal for Controlling Servos
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7.6 BASYS/Nexys-2 Board Examples |
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Verilog Examples |
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Example 56 – Loading Switch Data into a Register
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Example 57 – Shifting Data into a Shift Register
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Example 58 – Scrolling the 7-Segment Display
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Example 59 – Fibonacci Sequence
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Problems |
| 8. State Machines |
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8.1 Mealy and Moore State Machines |
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8.2 A Moore Machine Sequence Detector |
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8.3 Mealy Machine Sequence Detector |
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Verilog Examples |
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Example 60 – Sequence Detector
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Example 61 – Door Lock Code
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Example 62 – Traffic Lights
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Problems |
| 9. Datapath and Control Unit |
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9.1 Verilog while Statement |
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Example 63 - GCD Algorithm - Part 1 |
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9.2 Datapaths and Control Units |
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Example 64 - GCD Algorithm - Part 2 |
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Example 65 - An Integer Square Root Algorithm |
| 10. Integrating the Datapath and Control Unit |
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Example 66 - GCD Algorithm - Part 3 |
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Example 67 - Integer Square Root - Part 2 |
| 11. Memory |
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Example 68 - A Verilog ROM |
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Example 69 - Distributed RAM/ROM |
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Example 70 - Block RAM/ROM |
| 12. VGA Controller |
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Example 71 - VGA Stripes |
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Example 72 - VGA PROM |
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Example 73 - Sprites in Block ROM |
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Example 74 - Screen Saver |
| 13. PS/2 Port |
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Example 75 - Keyboard |
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Example 76 - Mouse |
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| Appendix A – Aldec Active-HDL Tutorial |
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Part 1: Project Setup |
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Part 2: Design Entry |
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Part 3: Simulation |
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Part 4: Creating a Top-level Design |
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Part 5: Synthesis and Implementation |
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Part 6: Program FPGA Board |
| Appendix B – Number Systems |
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B.1 Counting in Binary and Hexadecimal |
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B.2 Positional Notation |
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B.3 Fractional Numbers |
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B.4 Number System Conversions |
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B.5 Negative Numbers |
| Appendix C – Making a Turnkey System |
| Appendix D – Digilent FPGA Board Comparison Chart |
| Appendix E – Installing the Xilinx Vivado WebPACK |
| Appendix F – Verilog Quick Reference Guide |
| Index |
