A major revolution in digital design has taken place over the past two decades. Field programmable gate arrays (FPGAs) can now contain over a million equivalent logic gates and tens of thousands of flip-flops. This means that it is not possible to use traditional methods of logic design involving the drawing of logic diagrams when the digital circuit may contain thousands of gates. The reality is that today digital systems are designed by writing software in the form of hardware description languages (HDLs). The most common HDLs used today are VHDL and Verilog. Both are in widespread use. When using these hardware description languages the designer typically describes the behavior of the logic circuit rather than writing traditional Boolean logic equations. Computer-aided design tools are used to both simulate the Verilog or VHDL design and to synthesize the design to actual hardware.

This book assumes no previous knowledge of digital design. You start at the beginning learning about basic gates, logic equations, Boolean algebra, and Karnaugh maps. In over 75 examples we show you how to design digital circuits using Verilog, simulate them, and synthesize the designs to a Xilinx FPGA on one of the following Digilent FPGA boards available from www.digilentinc.com: the Basys™2 Spartan- 3E FPGA board, the Nexys™2 Spartan-3E FPGA board, the Nexys™3 Spartan-6 FPGA board, the Nexys™4 Artix-7 FPGA board, or the Basys3™ Artix-7 FPGA board. The differences between these boards are summarized in Appendix C. To simulate and synthesize your designs to a Xilinx FPGA, you will need to download the free Vivado HL WebPACK from Xilinx, Inc. (www.xilinx.com). A tutorial on using Vivado is given in Appendix A. Each of the FPGA boards will need its unique user constraints file (.ucf), which identifies specific pin numbers for a particular board (see Appendix C). You can download these .ucf files from http://www.lbebooks.com/downloads.htm.

The simulation examples given in this book used the Aldec Active-HDL simulator. A free student edition of the Aldec Active-HDL simulator is available from Aldec, Inc. (www.aldec.com). If you would like to use that simulator to simulate your designs, a tutorial is available on http://www.lbebooks.com.

Many colleagues and students have influenced the development of this book. Their stimulating discussions, probing questions, and critical comments are greatly appreciated.

You can download the source code for all 76 Verilog examples in this book by going to URL listed in the book. There are also instructional tips and resources available for instructors who adopt the book.

Richard E. Haskell
Darrin M. Hanna